A major challenge to make high-k metal oxides as gate dielectric successful in gate stacks for transistors is finding appropriate electrodes with stable band-edge Effective Work Functions (EWF) in order to meet the threshold voltage (VT) specifications for a gate stack in silicon technology as defined by the International Roadmap for Semiconductors (ITRS). For NMOS transistors the EWF of the gate stack needs to be high (closer to the Si conduction band edge) and for PMOS stacks, the EWF needs to be low (closer to the Si valence band edge). For NMOS devices a gate dielectric is deposited over a p-type gate region of a semiconductor substrate. In the on-state of the NMOS transistor, an n-type conductive channel is formed in the p-type gate area, between the n-type source and drain regions. For PMOS devices a gate dielectric is formed over an n-type gate region. One of the techniques known in the art for adjusting the EWF of the gate stack is adjusting the composition of the metal electrode; see e.g. US Patent Application Publication 2004/0106261 and U.S. Pat. No. 6,846,734. The value of the EWF of a gate stack is influenced by the electronegativity of the different elements and compounds composing the gate stack. Adding elements or compounds, which are more electronegative/electropositive than the host high-k dielectric tends to shift the EWF in positive/negative direction respectively. More recently, capping of the gate dielectric by using ultra-thin dielectric cap layer has been used to tune the EWF of the gate stack towards the desired values, e.g. IEEE Electron. Dev. Lett. 28(6), 486-488 (2007); IEEE Transactions on Electron. Dev. 54(10) 2738-2749 (2007); ECS Transactions 11(7) 201-211 (2007); ECS Transactions 19(1) 253-261, (2009). Typically, La based dielectric caps are used for NMOS and Al based caps for PMOS. The VFB shift with Al2O3 capping layers is only about 200 mV and not meeting requirements for 32 nm High Performance (HP) PMOS logic transistors. When increasing the thickness of the Al2O3 film, the VT shift only hardly increases and, because of the low k value of the Al2O3 layer, the EOT penalty significantly increases, which is unacceptable. Alternative cap layers are desirable, in particular for PMOS devices.